`timescale 1 ns / 1 ps
/*------------------- include --------------------*/

/*---------------------------------------------*/

`define CLOCK_FREQ_MHz 50.0   //系统主频 MHz

module tb; 

reg clk ; 

reg rst_n;          //复位信号
reg [7:0] isr ;

//生成时钟
parameter NCLK = 1000/`CLOCK_FREQ_MHz; 
initial begin
	clk=0;
	forever clk=#(NCLK/2) ~clk; 
end 

initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, tb);   //dumpvars(深度, 实例化模块1，实例化模块2，.....)
end


initial begin
	isr=8'h55;
	forever begin
        isr = #(NCLK*200) ~isr;
    end
end 


/*----------------------------- 模块 ------------------------------*/
cpsm_soc u_cpsm_soc(
    .clk( clk ),
    .rst_n(rst_n) , 
    .gpio0() , 
    .gpio1() , 
    .isr(isr)
);



//状态监控
integer dlt  = 0 ;
always@ (posedge clk) begin
    if(u_cpsm_soc.write_strobe)begin //
        case(u_cpsm_soc.port_id)
            8'h05:  begin 
                // $display("-> %d ns | dltTime %d ns: %d freq:%dMHz",$time ,$time - dlt  ,$signed(speed) , `CLOCK_FREQ_MHz) ;
                dlt = $time;
            end 
        endcase 
    end 
end  

initial begin
    $display(" -------- cpsm_soc sim ----------");
    rst_n = 0;
    repeat(2) @(posedge clk) ;
    rst_n = 1 ; 
    repeat(5000) @(posedge clk) ;

    $display("%d ns:done",$time);
	$dumpflush;
	$finish;
	$stop;	
end

endmodule
